Datasheet
Operation Mode Truth Table
Notes 1, 2, 3 and 4 apply to the entire Command Truth Table.
Note 5 Applies to all Read/Write commands.
[BG=Bank Group Address, BA=Bank Address, RA=Row Address, CA=Column Address, BC#=Burst Chop, X=Don’t Care, V=Valid].
Table 5. Command Truth Table
Function
Symbol
CKE
n-1
CKE
n
CS#
ACT#
RAS#
/A16
CAS#
/A15
WE#/
A14
BG
0-1
BA
0-1
BC#/
A12
A13,
A11
A10/
AP
A0-A9
Mode Register Set
MRS
H
H
L
H
L
L
L
BG
BA
OP Code
Refresh
REF
H
H
L
H
L
L
H
V
V
V
V
V
V
Self Refresh Entry
7,9
SRE
H
L
L
H
L
L
H
V
V
V
V
V
V
Self Refresh Exit
7-10
SRX
L
H
H
X
X
X
X
X
X
X
X
X
X
L
H
H
H
H
V
V
V
V
V
V
Single Bank Precharge
PRE
H
H
L
H
L
H
L
BG
BA
V
V
L
V
Precharge all Banks
PREA
H
H
L
H
L
H
L
V
V
V
V
H
V
RFU
RFU
H
H
L
H
L
H
H
RFU
RFU
RFU
RFU
RFU
RFU
Bank Activate
ACT
H
H
L
L
RA
RA
RA
BG
BA
RA
RA
RA
RA
Write (Fixed BL8 or BC4)
WR
H
H
L
H
H
L
L
BG
BA
V
V
L
CA
Write (BC4, on the Fly)
WRS4
H
H
L
H
H
L
L
BG
BA
L
V
L
CA
Write (BL8, on the Fly)
WRS8
H
H
L
H
H
L
L
BG
BA
H
V
L
CA
Write with Auto Precharge
(Fixed BL8 or BC4)
WRA
H
H
L
H
H
L
L
BG
BA
V
V
H
CA
Write with Auto Precharge
(BC4, on the Fly)
WRAS4
H
H
L
H
H
L
L
BG
BA
L
V
H
CA
Write with Auto Precharge
(BL8, on the Fly)
WRAS8
H
H
L
H
H
L
L
BG
BA
H
V
H
CA
Read (Fixed BL8 or BC4)
RD
H
H
L
H
H
L
H
BG
BA
V
V
L
CA
Read (BC4, on the Fly)
RDS4
H
H
L
H
H
L
H
BG
BA
L
V
L
CA
Read (BL8, on the Fly)
RDS8
H
H
L
H
H
L
H
BG
BA
H
V
L
CA
Read with Auto Precharge
(Fixed BL8 or BC4)
RDA
H
H
L
H
H
L
H
BG
BA
V
V
H
CA
Read with Auto Precharge
(BC4, on the Fly)
RDAS4
H
H
L
H
H
L
H
BG
BA
L
V
H
CA
Read with Auto Precharge
(BL8, on the Fly)
RDAS8
H
H
L
H
H
L
H
BG
BA
H
V
H
CA
No Operation
NOP
H
H
L
H
H
H
H
V
V
V
V
V
V
Device Deselected
DES
H
H
H
X
X
X
X
X
X
X
X
X
X
Power Down Entry
6
PDE
H
L
H
X
X
X
X
X
X
X
X
X
X
Power Down Exit
6
PDX
L
H
H
X
X
X
X
X
X
X
X
X
X
ZQ calibration Long
ZQCL
H
H
L
H
H
H
L
V
V
V
V
H
V
ZQ calibration Short
ZQCS
H
H
L
H
H
H
L
V
V
V
V
L
V
Note 1. All DDR4 SDRAM commands are defined by states of CS#, ACT#, RAS#/A16, CAS#/A15, WE#/A14 and CKE at the rising edge of the clock. The
MSB of BG, BA, RA and CA are device density and configuration dependent. When ACT# = H; pins RAS#/A16, CAS#/A15, and WE#/A14 are used
as command pins RAS#, CAS#, and WE# respectively. When ACT# = L; pins RAS#/A16, CAS#/A15, and WE#/A14 are used as address pins A16,
A15, and A14 respectively.
Note 2. Reset# is low enable command which will be used only for asynchronous reset so must be maintained high during any function.
Note 3. Bank Group addresses (BG) and Bank addresses (BA) determine which bank within a bank group to be operated upon. For MRS commands the BG
and BA selects the specific Mode Register location.
Note 4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.
Note 5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.
Note 6. The Power Down Mode does not perform any refresh operation.
Note 7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
Note 8. Controller guarantees self refresh exit to be synchronous.
Note 9. V
PP
and V
REF
(V
REFCA
) must be maintained during Self Refresh operation.
Note 10. The No Operation (NOP) command may be used only when exiting maximum power saving mode or when entering gear-down mode.
Note 11. Refer to the CKE Truth Table for more detail with CKE transition.
AS4C512M8D4
Confidential
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Rev.1.0. Aug.2019