Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Table 58: DDR3L-800/1066 Derating Values
t
IS/
t
IH – AC160/DC90-Based
Δ
Δ
t
IS,
Δ
t
IH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
2.0 80 45 80 45 80 45 88 53 96 61 104 69 112 79 120 95
1.5 53 30 53 30 53 30 61 38 69 46 77 54 85 64 93 80
1.0 0 0 0 0
00
8 8 16 16 24 24 32 34 40 50
0.9 –1 –3 –1 –3
–1 –3
7 5 15 13 23 21 31 31 39 47
0.8 –3 –8 –3 –8 –3 –8 5 1 13 9 21 17 29 27 37 43
0.7 –5 –13 –5 –13 –5 –13 3 –5 11 3 19 11 27 21 35 37
0.6 –8 –20 –8 –20 –8 –20 0 –12 8 –4 16 4 24 14 32 30
0.5 –20 –30 –20 –30 –20 –30 –12 –22 –4 –14 4 –6 12 4 20 20
0.4 –40 –45 –40 –45 –40 –45 –32 –37 –24 –29 –16 –21 –8 –11 0 5
Table 59: DDR3L-800/1066/1333/1600 Derating Values for
t
IS/
t
IH – AC135/DC90-Based
Δ
t
IS,
Δ
t
IH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
2.0 68 45 68 45 68 45 76 53 84 61 92 69 100 79 108 95
1.5 45 30 45 30 45 30 53 38 61 46 69 54 77 64 85 80
1.0 0 0 0 0
00
8 8 16 16 24 24 32 34 40 50
0.9 2 –3 2 –3
2–3
10 5 1813262134314247
0.8 3 –8 3 –8 3 –8 11 1 19 9 27 17 35 27 43 43
0.7 6 –13 6 –13 6 –13 14 –5 22 3 30 11 38 21 46 37
0.6 9 –20 9 –20 9 –20 17 –12 25 –4 33 4 41 14 49 30
0.5 5 –30 5 –30 5 –30 13 –22 21 –14 29 –6 37 4 45 20
0.4 –3 –45 –3 –45 –3 –45 6 –37 14 –29 22 –21 30 –11 38 5
Table 60: DDR3L-1866/2133 Derating Values for
t
IS/
t
IH – AC125/DC90-Based
Δ
t
IS,
Δ
t
IH Derating (ps) – AC/DC-Based
CMD/ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
Δ
t
IS
Δ
t
IH
2.0 63 45 63 45 63 45 71 53 79 61 87 69 95 79 103 95
1.5 42 30 42 30 42 30 50 38 58 46 66 54 74 64 82 80
1.0 0 0 0 0
00
8 8 16 16 24 24 32 34 40 50
8Gb: x4, x8, x16 DDR3L SDRAM
Command and Address Setup, Hold, and Derating
94
Rev 2.0 June 2016
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