Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866 DDR3L-2133
Unit NotesMin Max Min Max
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4 MIN = 4; MAX = N/A CK
Dynamic ODT Timing
R
TT,nom
-to-R
TT(WR)
change skew ODTLcnw WL - 2CK CK
R
TT(WR)
-to-R
TT,nom
change skew - BC4 ODTLcwn4 4CK + ODTLoff CK
R
TT(WR)
-to-R
TT,nom
change skew - BL8 ODTLcwn8 6CK + ODTLoff CK
R
TT
dynamic change skew
t
ADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge
t
WLMRD 40 – 40 – CK
DQS, DQS# delay
t
WLDQSEN 25 – 25 – CK
Write leveling setup from rising CK, CK#
crossing to rising DQS, DQS# crossing
t
WLS 140 – 125 – ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
t
WLH 140 – 125 – ps
Write leveling output delay
t
WLO 0 7.5 0 7 ns
Write leveling output error
t
WLOE 0 2 0 2 ns
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
89
Rev 2.0 June 2016
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