Datasheet

Figure 103: MRS Command to Power-Down Entry ......................................................................................... 183
Figure 104: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 184
Figure 105: RESET Sequence ......................................................................................................................... 186
Figure 106: On-Die Termination ................................................................................................................... 187
Figure 107: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 192
Figure 108: Dynamic ODT: Without WRITE Command .................................................................................. 192
Figure 109: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 193
Figure 110: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 194
Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 194
Figure 112: Synchronous ODT ...................................................................................................................... 196
Figure 113: Synchronous ODT (BC4) ............................................................................................................. 197
Figure 114: ODT During READs .................................................................................................................... 199
Figure 115: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 201
Figure 116: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 203
Figure 117: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 205
Figure 118: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 207
Figure 119: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 207
8Gb: x4, x8, x16 DDR3L SDRAM
Description
8
Rev 2.0 June 2016
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