Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866 DDR3L-2133
Unit NotesMin Max Min Max
REFRESH-to-ACTIVATE or REFRESH
command period
t
RFC – 1Gb MIN = 110; MAX = 70,200 ns
t
RFC – 2Gb MIN = 160; MAX = 70,200 ns
t
RFC – 4Gb MIN = 260; MAX = 70,200 ns
t
RFC – 8Gb MIN = 350; MAX = 70,200 ns
Maximum refresh
period
T
C
≤ 85°C – 64 (1X) ms 36
T
C
> 85°C 32 (2X) ms 36
Maximum average
periodic refresh
T
C
≤ 85°C
t
REFI 7.8 (64ms/8192) μs 36
T
C
> 85°C 3.9 (32ms/8192) μs 36
Self Refresh Timing
Exit self refresh to commands not requiring a
locked DLL
t
XS MIN = greater of 5CK or
t
RFC + 10ns; MAX = N/A CK
Exit self refresh to commands requiring a
locked DLL
t
XSDLL MIN =
t
DLLK (MIN);
MAX = N/A
CK 28
Minimum CKE low pulse width for self re-
fresh entry to self refresh exit timing
t
CKESR MIN =
t
CKE (MIN) + CK; MAX = N/A CK
Valid clocks after self refresh entry or power-
down entry
t
CKSRE MIN = greater of 5CK or 10ns; MAX = N/A CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
t
CKSRX MIN = greater of 5CK or 10ns; MAX = N/A CK
Power-Down Timing
CKE MIN pulse width
t
CKE (MIN) Greater of 3CK or 5ns CK
Command pass disable delay
t
CPDED MIN = 2;
MAX = N/A
CK
Power-down entry to power-down exit tim-
ing
t
PD MIN =
t
CKE (MIN);
MAX = 9 * tREFI
CK
Begin power-down period prior to CKE
registered HIGH
t
ANPD WL - 1CK CK
Power-down entry period: ODT either
synchronous or asynchronous
PDE Greater of
t
ANPD or
t
RFC - REFRESH command to CKE LOW time CK
Power-down exit period: ODT either
synchronous or asynchronous
PDX
t
ANPD +
t
XPDLL CK
Power-Down Entry Minimum Timing
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
87
Rev 2.0 June 2016
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