Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Table 56: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-1866 DDR3L-2133
Unit NotesMin Max Min Max
DQS, DQS# differential input high pulse
width
t
DQSH 0.45 0.55 0.45 0.55 CK
DQS, DQS# falling setup to CK, CK# rising
t
DSS 0.18 – 0.18 – CK 25
DQS, DQS# falling hold from CK, CK# rising
t
DSH 0.18 – 0.18 – CK 25
DQS, DQS# differential WRITE preamble
t
WPRE 0.9 – 0.9 – CK
DQS, DQS# differential WRITE postamble
t
WPST 0.3 – 0.3 – CK
DQ Strobe Output Timing
DQS, DQS# rising to/from rising CK, CK#
t
DQSCK –195 195 –180 180 ps 23
DQS, DQS# rising to/from rising CK, CK#
when DLL is disabled
t
DQSCK
(DLL_DIS)
1 10 1 10 ns 26
DQS, DQS# differential output high time
t
QSH 0.40 – 0.40 – CK 21
DQS, DQS# differential output low time
t
QSL 0.40 – 0.40 – CK 21
DQS, DQS# Low-Z time (RL - 1)
t
LZDQS –390 195 –360 180 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2)
t
HZDQS – 195 – 180 ps 22, 23
DQS, DQS# differential READ preamble
t
RPRE 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble
t
RPST 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time
t
DLLK 512 – 512 – CK 28
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC135)
65 – 60 – ps 29, 30,
44
V
REF
@ 1 V/ns 200 – 195 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC125)
150 – 135 – ps 29, 30,
44
V
REF
@ 1 V/ns 275 – 260 – ps 20, 30
CTRL, CMD, ADDR hold
from CK,CK#
Base (specification)
t
IH
(DC90)
110 – 95 – ps 29, 30
V
REF
@ 1 V/ns 200 – 195 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width
t
IPW 535 – 470 – ps 41
ACTIVATE to internal READ or WRITE delay
t
RCD See Speed Bin Tables for
t
RCD ns 31
PRECHARGE command period
t
RP See Speed Bin Tables for
t
RP ns 31
ACTIVATE-to-PRECHARGE command period
t
RAS See Speed Bin Tables for
t
RAS ns 31, 32
ACTIVATE-to-ACTIVATE command period
t
RC See Speed Bin Tables for
t
RC ns 31, 43
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
85
Rev 2.0 June 2016
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