Datasheet

Figure 51: READ Latency .............................................................................................................................. 134
Figure 52: Mode Register 1 (MR1) Definition ................................................................................................. 135
Figure 53: READ Latency (AL = 5, CL = 6) ....................................................................................................... 138
Figure 54: Mode Register 2 (MR2) Definition ................................................................................................. 139
Figure 55: CAS WRITE Latency ...................................................................................................................... 139
Figure 56: Mode Register 3 (MR3) Definition ................................................................................................. 141
Figure 57: Multipurpose Register (MPR) Block Diagram ................................................................................. 142
Figure 58: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 145
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 146
Figure 60: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 147
Figure 61: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 148
Figure 62: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 150
Figure 63: Example: Meeting
t
RRD (MIN) and
t
RCD (MIN) ............................................................................. 151
Figure 64: Example:
t
FAW ............................................................................................................................. 152
Figure 65: READ Latency .............................................................................................................................. 153
Figure 66: Consecutive READ Bursts (BL8) .................................................................................................... 155
Figure 67: Consecutive READ Bursts (BC4) .................................................................................................... 155
Figure 68: Nonconsecutive READ Bursts ....................................................................................................... 156
Figure 69: READ (BL8) to WRITE (BL8) .......................................................................................................... 156
Figure 70: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 157
Figure 71: READ to PRECHARGE (BL8) .......................................................................................................... 157
Figure 72: READ to PRECHARGE (BC4) ......................................................................................................... 158
Figure 73: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 158
Figure 74: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 158
Figure 75: Data Output Timing –
t
DQSQ and Data Valid Window .................................................................... 160
Figure 76: Data Strobe Timing – READs ......................................................................................................... 161
Figure 77: Method for Calculating
t
LZ and
t
HZ ............................................................................................... 162
Figure 78:
t
RPRE Timing ............................................................................................................................... 162
Figure 79:
t
RPST Timing ............................................................................................................................... 163
Figure 80:
t
WPRE Timing .............................................................................................................................. 165
Figure 81:
t
WPST Timing .............................................................................................................................. 165
Figure 82: WRITE Burst ................................................................................................................................ 166
Figure 83: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 167
Figure 84: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 167
Figure 85: Nonconsecutive WRITE to WRITE ................................................................................................. 168
Figure 86: WRITE (BL8) to READ (BL8) .......................................................................................................... 168
Figure 87: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 169
Figure 88: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 170
Figure 89: WRITE (BL8) to PRECHARGE ........................................................................................................ 171
Figure 90: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 171
Figure 91: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 172
Figure 92: Data Input Timing ........................................................................................................................ 173
Figure 93: Self Refresh Entry/Exit Timing ...................................................................................................... 175
Figure 94: Active Power-Down Entry and Exit ................................................................................................ 179
Figure 95: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 179
Figure 96: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 180
Figure 97: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 180
Figure 98: Power-Down Entry After WRITE .................................................................................................... 181
Figure 99: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 181
Figure 100: REFRESH to Power-Down Entry .................................................................................................. 182
Figure 101: ACTIVATE to Power-Down Entry ................................................................................................. 182
Figure 102: PRECHARGE to Power-Down Entry ............................................................................................. 183
8Gb: x4, x8, x16 DDR3L SDRAM
Description
7
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
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