Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Table 55: Electrical Characteristics and AC Operating Conditions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600
Unit NotesMin Max Min Max Min Max Min Max
DQS, DQS# Low-Z time (RL - 1)
t
LZDQS –800 400 –600 300 –500 250 –450 225 ps 22, 23
DQS, DQS# High-Z time (RL + BL/2)
t
HZDQS – 400 – 300 – 250 – 225 ps 22, 23
DQS, DQS# differential READ preamble
t
RPRE 0.9 Note 24 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23, 24
DQS, DQS# differential READ postamble
t
RPST 0.3 Note 27 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23, 27
Command and Address Timing
DLL locking time
t
DLLK 512 – 512 – 512 – 512 – CK 28
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC160)
215 – 140 – 80 – 60 – ps 29, 30,
44
V
REF
@ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IS
(AC135)
365 – 290 – 205 – 185 – ps 29, 30,
44
V
REF
@ 1 V/ns 500 – 425 – 340 – 320 – ps 20, 30
CTRL, CMD, ADDR
setup to CK,CK#
Base (specification)
t
IH
(DC90
285 – 210 – 150 – 130 – ps 29, 30,
44
V
REF
@ 1 V/ns 375 – 300 – 240 – 220 – ps 20, 30
Minimum CTRL, CMD, ADDR pulse width
t
IPW 900 – 780 – 620 – 560 – ps 41
ACTIVATE to internal READ or WRITE delay
t
RCD See Speed Bin Tables for
t
RCD ns 31
PRECHARGE command period
t
RP See Speed Bin Tables for
t
RP ns 31
ACTIVATE-to-PRECHARGE command period
t
RAS See Speed Bin Tables for
t
RAS ns 31, 32
ACTIVATE-to-ACTIVATE command period
t
RC See Speed Bin Tables for
t
RC ns 31, 43
ACTIVATE-to-ACTIVATE
minimum command
period
x4/x8/x16
(2KB page size)
t
RRD MIN = greater of 4CK or 10ns MIN = greater of 4CK or 7.5ns CK 31
Four ACTIVATE
windows
x4/x8/x16
(2KB page size)
t
FAW50–50–45–40–ns31
Write recovery time
t
WR MIN = 15ns; MAX = N/A ns 31, 32,
33,34
Delay from start of internal WRITE
transaction to internal READ command
t
WTR MIN = greater of 4CK or 7.5ns; MAX = N/A CK 31, 34
READ-to-PRECHARGE time
t
RTP MIN = greater of 4CK or 7.5ns; MAX = N/A CK 31, 32
CAS#-to-CAS# command delay
t
CCD MIN = 4CK; MAX = N/A CK
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Characteristics and AC Operating Conditions
75
Rev 2.0 June 2016
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