Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Slew Rate Definitions for Differential Output Signals
The differential output driver is summarized in Table 46 (page 63). With the reference
load for timing measurements, the output slew rate for falling and rising edges is de-
fined and measured between V
OL(AC)
and V
OH(AC)
for differential signals.
Table 49: Differential Output Slew Rate Definition
Differential Output Slew
Rates (Linear Signals)
Measured
CalculationOutput Edge From To
DQS, DQS# Rising V
OL,diff(AC)
V
OH,diff(AC)
V
OH,diff(AC)
- V
OL,diff(AC)
ΔTR
diff
Falling V
OH,diff(AC)
V
OL,diff(AC)
V
OH,diff(AC)
- V
OL,diff(AC)
ΔTF
diff
Figure 29: Nominal Differential Output Slew Rate Definition for DQS, DQS#
ΔTR
diff
ΔTF
diff
V
OH,diff(AC)
V
OL,diff(AC)
0
8Gb: x4, x8, x16 DDR3L SDRAM
Output Characteristics and Operating Conditions
67
Rev 2.0 June 2016
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