Datasheet

Figure 25: DQ Output Signal
V
OH(AC)
MIN output
MAX output
V
OL(AC)
Table 46: DDR3L Differential Output Driver Characteristics
All voltages are referenced to V
SS
Parameter/Condition Symbol Min Max Unit Notes
Output leakage current: DQ are disabled;
0V ≤ V
OUT
≤ V
DDQ
; ODT is disabled; ODT is HIGH
I
OZ
–5 5 μA 1
DDR3L Output slew rate: Differential; For rising and fall-
ing edges, measure between V
OL,diff(AC)
= –0.18 × V
DDQ
and V
OH,diff(AC)
= 0.18 × V
DDQ
SRQ
diff
3.5 12 V/ns 1
Differential high-level output voltage V
OH,diff(AC)
+0.2 × V
DDQ
V 1, 4
Differential low-level output voltage V
OL,diff(AC)
–0.2 × V
DDQ
V 1, 4
Delta Ron between pull-up and pull-down for DQ/DQS MM
PUPD
–10 10 % 1, 5
Test load for AC timing and output slew rates Output to V
TT
(V
DDQ
/2) via 25Ω resistor 3
Notes:
1. RZQ of 240Ω ±1% with RZQ/7 enabled (default 34Ω driver) and is applicable after prop-
er ZQ calibration has been performed at a stable temperature and voltage (V
DDQ
= V
DD
;
V
SSQ
= V
SS
).
2. V
REF
= V
DDQ
/2; slew rate @ 5 V/ns, interpolate for faster slew rate.
3. See Figure 27 (page 65) for the test load configuration.
4. See Table 49 (page 67) for the output slew rate.
5. See Table 35 (page 57) for additional information.
6. See Figure 26 (page 64) for an example of a differential output signal.
8Gb: x4, x8, x16 DDR3L SDRAM
Output Characteristics and Operating Conditions
63
Rev 2.0 June 2016
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