Datasheet

Figure 20: ODT Timing Reference Load
Timing reference point
DQ, DM
DQS, DQS#
TDQS, TDQS#
DUT
V
REF
V
TT
= V
SSQ
V
DDQ
/2
ZQ
RZQ = 240Ω
V
SSQ
R
TT
= 25Ω
CK, CK#
Table 33: ODT Timing Definitions
Symbol Begin Point Definition End Point Definition Figure
t
AON Rising edge of CK – CK# defined by the end
point of ODTLon
Extrapolated point at V
SSQ
Figure 21 (page 54)
t
AOF Rising edge of CK – CK# defined by the end
point of ODTLoff
Extrapolated point at V
RTT,nom
Figure 21 (page 54)
t
AONPD Rising edge of CK – CK# with ODT first being
registered HIGH
Extrapolated point at V
SSQ
Figure 22 (page 54)
t
AOFPD Rising edge of CK – CK# with ODT first being
registered LOW
Extrapolated point at V
RTT,nom
Figure 22 (page 54)
t
ADC Rising edge of CK – CK# defined by the end
point of ODTLcnw, ODTLcwn4, or ODTLcwn8
Extrapolated points at V
RTT(WR)
and
V
RTT,nom
Figure 23 (page 55)
Table 34: DDR3L(1.35V) Reference Settings for ODT Timing Measurements
Measured
Parameter
R
TT,nom
Setting R
TT(WR)
Setting V
SW1
V
SW2
t
AON RZQ/4 (60Ω N/A 50mV 100mV
RZQ/12 (20Ω N/A 100mV 200mV
t
AOF RZQ/4 (60Ω N/A 50mV 100mV
RZQ/12 (20Ω N/A 100mV 200mV
t
AONPD RZQ/4 (60Ω N/A 50mV 100mV
RZQ/12 (20Ω N/A 100mV 200mV
t
AOFPD RZQ/4 (60Ω N/A 50mV 100mV
RZQ/12 (20Ω N/A 100mV 200mV
t
ADC RZQ/12 (20Ω RZQ/2 (20Ω 200mV 250mV
8Gb: x4, x8, x16 DDR3L SDRAM
ODT Characteristics
53
Rev 2.0 June 2016
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