Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

DDR3L 1.35V Slew Rate Definitions for Single-Ended Input Signals
Setup (
t
IS and
t
DS) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of V
REF
and the first crossing of V
IH(AC)min
. Setup (
t
IS and
t
DS)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V
REF
and the first crossing of V
IL(AC)max
.
Hold (
t
IH and
t
DH) nominal slew rate for a rising signal is defined as the slew rate be-
tween the last crossing of V
IL(DC)max
and the first crossing of V
REF
. Hold (
t
IH and
t
DH)
nominal slew rate for a falling signal is defined as the slew rate between the last crossing
of V
IH(DC)min
and the first crossing of V
REF
(see Figure 17 (page 48)).
Table 27: Single-Ended Input Slew Rate Definition
Input Slew Rates
(Linear Signals)
Measured
CalculationInput Edge From To
Setup
Rising V
REF
V
IH(AC),min
V
IH(AC),min
- V
REF
ΔTRS
se
Falling V
REF
V
IL(AC),max
V
REF
- V
IL(AC),max
ΔTFS
se
Hold
Rising V
IL(DC),max
V
REF
V
REF
- V
IL(DC),max
ΔTFH
se
Falling V
IH(DC),min
V
REF
V
IH(DC),min
- V
REF
ΔTRSH
se
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
47
Rev.2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211