Datasheet

Figure 16: Definition of Differential AC-Swing and
t
DVAC
V
IH,diff(AC)min
0.0
V
IL,diff,max
t
DVAC
V
IH,diff,min
V
IL,diff(AC)max
Half cycle
t
DVAC
CK - CK#
DQS - DQS#
Table 26: DDR3L 1.35V – Minimum Required Time
t
DVAC for CK/CK#, DQS/DQS# Differential for AC
Ringback
Slew Rate (V/ns)
DDR3L-800/1066/1333/1600 DDR3L-1866/2133
t
DVAC at
320mV (ps)
t
DVAC at
270mV (ps)
t
DVAC at
270mV (ps)
t
DVAC at
250mV (ps)
t
DVAC at
260mV (ps)
>4.0 189 201 163 168 176
4.0 189 201 163 168 176
3.0 162 179 140 147 154
2.0 109 134 95 105 111
1.8 91 119 80 91 97
1.6 69 100 62 74 78
1.4 40 76 37 52 55
1.2 Note 1 44 5 22 24
1.0 Note 1
<1.0 Note 1
Note:
1. Rising input signal shall become equal to or greater than V
IH(AC)
level and Falling input
signal shall become equal to or less than V
IL(AC)
level.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
46
Rev.2.0 June 2016
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