Datasheet

Table Of Contents
Table 23: DDR3L 1.35V Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition Symbol Min Max Units Notes
Differential input logic high – slew V
IH,diff(AC)slew
180 N/A mV 4
Differential input logic low – slew V
IL,diff(AC)slew
N/A –180 mV 4
Differential input logic high V
IH,diff(AC)
2 × (V
IH(AC)
- V
REF
)V
DD
/V
DDQ
mV 5
Differential input logic low V
IL,diff(AC)
V
SS
/V
SSQ
2 × (V
IL(AC)
- V
REF
)mV 6
Differential input crossing voltage
relative to V
DD
/2 for DQS, DQS#; CK,
CK#
V
IX
V
REF(DC)
- 150 V
REF(DC)
+ 150 mV 5, 7, 9
Differential input crossing voltage
relative to V
DD
/2 for CK, CK#
V
IX
(175) V
REF(DC)
- 175 V
REF(DC)
+ 175 mV 5, 7–9
Single-ended high level for strobes
V
SEH
V
DDQ
/2 + 160 V
DDQ
mV 5
Single-ended high level for CK, CK# V
DD
/2 + 160 V
DD
mV 5
Single-ended low level for strobes
V
SEL
V
SSQ
V
DDQ
/2 - 160 mV 6
Single-ended low level for CK, CK# V
SS
V
DD
/2 - 160 mV 6
Notes:
1. Clock is referenced to V
DD
and V
SS
. Data strobe is referenced to V
DDQ
and V
SSQ
.
2. Reference is V
REFCA(DC)
for clock and V
REFDQ(DC)
for strobe.
3. Differential input slew rate = 2 V/ns.
4. Defines slew rate reference points, relative to input crossing voltages.
5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-
cable.
6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-
plicable.
7. The typical value of V
IX(AC)
is expected to be about 0.5 × V
DD
of the transmitting device,
and V
IX(AC)
is expected to track variations in V
DD
. V
IX(AC)
indicates the voltage at which
differential input signals must cross.
8. The V
IX
extended range (±175mV) is allowed only for the clock; this V
IX
extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing V
SEL
, V
SEH
of at least V
DD
/2 ±250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
9. V
IX
must provide 25mV (single-ended) of the voltages separation.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
42
Rev.2.0 June 2016
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