Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Input Operating Conditions
Table 21: DDR3L 1.35V DC Electrical Characteristics and Input Conditions
All voltages are referenced to V
SS
Parameter/Condition Symbol Min Nom Max Unit Notes
V
IN
low; DC/commands/address busses V
IL
V
SS
N/A See Table 22 V
V
IN
high; DC/commands/address busses V
IH
See Table 22 N/A V
DD
V
Input reference voltage command/address bus V
REFCA(DC)
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 1, 2
I/O reference voltage DQ bus V
REFDQ(DC)
0.49 × V
DD
0.5 × V
DD
0.51 × V
DD
V 2, 3
I/O reference voltage DQ bus in SELF REFRESH V
REFDQ(SR)
V
SS
0.5 × V
DD
V
DD
V4
Command/address termination voltage
(system level, not direct DRAM input)
V
TT
– 0.5 × V
DDQ
–V5
Notes:
1. V
REFCA(DC)
is expected to be approximately 0.5 × V
DD
and to track variations in the DC
level. Externally generated peak noise (non-common mode) on V
REFCA
may not exceed
±1% × V
DD
around the V
REFCA(DC)
value. Peak-to-peak AC noise on V
REFCA
should not ex-
ceed ±2% of V
REFCA(DC)
.
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifi-
cations if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. V
REFDQ(DC)
is expected to be approximately 0.5 × V
DD
and to track variations in the DC
level. Externally generated peak noise (non-common mode) on V
REFDQ
may not exceed
±1% × V
DD
around the V
REFDQ(DC)
value. Peak-to-peak AC noise on V
REFDQ
should not ex-
ceed ±2% of V
REFDQ(DC)
.
4. V
REFDQ(DC)
may transition to V
REFDQ(SR)
and back to V
REFDQ(DC)
when in SELF REFRESH,
within restrictions outlined in the SELF REFRESH section.
5. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination re-
sistors. Minimum and maximum values are system-dependent.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – DC and AC
40
Rev.2.0 June 2016
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