Datasheet

Table 17: I
DD
Measurement Conditions for I
DD6
, I
DD6ET
, and I
DD8
I
DD
Test
I
DD6
: Self Refresh Current
Normal Temperature Range
T
C
= 0°C to +85°C
I
DD6ET
: Self Refresh Current
Extended Temperature Range
T
C
= 0°C to +95°C I
DD8
: Reset
2
CKE LOW LOW Midlevel
External clock Off, CK and CK# = LOW Off, CK and CK# = LOW Midlevel
t
CK N/A N/A N/A
t
RC N/A N/A N/A
t
RAS N/A N/A N/A
t
RCD N/A N/A N/A
t
RRD N/A N/A N/A
t
RC N/A N/A N/A
CL N/A N/A N/A
AL N/A N/A N/A
CS# Midlevel Midlevel Midlevel
Command inputs Midlevel Midlevel Midlevel
Row/column addresses Midlevel Midlevel Midlevel
Bank addresses Midlevel Midlevel Midlevel
Data I/O Midlevel Midlevel Midlevel
Output buffer DQ, DQS Enabled Enabled Midlevel
ODT
1
Enabled, midlevel Enabled, midlevel Midlevel
Burst length N/A N/A N/A
Active banks N/A N/A None
Idle banks N/A N/A All
SRT Disabled (normal) Enabled (extended) N/A
ASR Disabled Disabled N/A
Notes:
1. “Enabled, midlevel” means the MR command is enabled, but the signal is midlevel.
2. During a cold boot RESET (initialization), current reading is valid after power is stable
and RESET has been LOW for 1ms; During a warm boot RESET (while operating), current
reading is valid after RESET has been LOW for 200ns +
t
RFC.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
35
Rev.2.0 June 2016
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