Datasheet

Table 16: I
DD5B
Measurement Loop
CK, CK#
CKE
Sub-Loop
Cycle Number
Command
CS#
RAS# CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7] A[6:3] A[2:0]
Data
Toggling
Static HIGH
0 0 REF 00010000000 –
1a
1 D 10000000000 –
2 D 10000000000 –
3 D# 111100000F0 –
4 D# 111100000F0 –
1b 5–8 Repeat sub-loop 1a, use BA[2:0] = 1
1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2
1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3
1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4
1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5
1g 25–28 Repeat sub-loop 1a, use BA[2:0] = 6
1h 29–32 Repeat sub-loop 1a, use BA[2:0] = 7
2 33–nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1; truncate if needed
Notes:
1. DQ, DQS, DQS# are midlevel.
2. DM is LOW.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
34
Rev.2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: [phone] FAX: [phone]