Datasheet

Table 15: I
DD4W
Measurement Loop
CK, CK#
CKE
Sub-Loop
Cycle Number
Command
CS#
RAS# CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7] A[6:3] A[2:0]
Data
4
Toggling
Static HIGH
0
0 WR 0 1 0 0 1 0 0 0 0 0 0 00000000
1 D 10001000000 –
2 D# 11111000000 –
3 D# 11111000000 –
4 WR 0 1 0 0 1 0 0 0 0 F 0 00110011
5 D 100010000F0 –
6 D# 111110000F0 –
7 D# 111110000F0 –
1 8–15 Repeat sub-loop 0, use BA[2:0] = 1
2 16–23 Repeat sub-loop 0, use BA[2:0] = 2
3 24–31 Repeat sub-loop 0, use BA[2:0] = 3
4 32–39 Repeat sub-loop 0, use BA[2:0] = 4
5 40–47 Repeat sub-loop 0, use BA[2:0] = 5
6 48–55 Repeat sub-loop 0, use BA[2:0] = 6
7 56–63 Repeat sub-loop 0, use BA[2:0] = 7
Notes:
1. DQ, DQS, DQS# are midlevel when not driving in burst sequence.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the WR command.
4. All banks open.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
33
Rev.2.0 June 2016
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