Datasheet

Table 11: I
DD
Measurement Conditions for Power-Down Currents
Name
I
DD2P0
Precharge
Power-Down
Current (Slow Exit)
1
I
DD2P1
Precharge
Power-Down
Current (Fast Exit)
1
I
DD2Q
Precharge
Quiet
Standby Current
I
DD3P
Active
Power-Down
Current
Timing pattern N/A N/A N/A N/A
CKE LOW LOW HIGH LOW
External clock Toggling Toggling Toggling Toggling
t
CK
t
CK (MIN) I
DD
t
CK (MIN) I
DD
t
CK (MIN) I
DD
t
CK (MIN) I
DD
t
RC N/A N/A N/A N/A
t
RAS N/A N/A N/A N/A
t
RCD N/A N/A N/A N/A
t
RRD N/A N/A N/A N/A
t
RC N/A N/A N/A N/A
CL N/A N/A N/A N/A
AL N/A N/A N/A N/A
CS# HIGH HIGH HIGH HIGH
Command inputs LOW LOW LOW LOW
Row/column addr LOW LOW LOW LOW
Bank addresses LOW LOW LOW LOW
DM LOW LOW LOW LOW
Data I/O Midlevel Midlevel Midlevel Midlevel
Output buffer DQ, DQS Enabled Enabled Enabled Enabled
ODT
2
Enabled, off Enabled, off Enabled, off Enabled, off
Burst length 8 8 8 8
Active banks None None None All
Idle banks All All All None
Special notes N/A N/A N/A N/A
Notes:
1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast
exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0).
2. “Enabled, off” means the MR bits are enabled, but the signal is LOW.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
30
Rev.2.0 June 2016
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