Datasheet

Table 10: I
DD1
Measurement Loop
CK, CK#
CKE
Sub-Loop
Cycle Number
Command
CS#
RAS# CAS#
WE#
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7] A[6:3] A[2:0]
Data
2
Toggling
Static HIGH
0
0 ACT 00110000000 –
1 D 10000000000 –
2 D 10000000000 –
3 D# 11110000000 –
4 D# 11110000000 –
Repeat cycles 1 through 4 until nRCD - 1; truncate if needed
nRCD RD 0 1 0 1 0 0 0 0 0 0 0 00000000
Repeat cycles 1 through 4 until nRAS - 1; truncate if needed
nRAS PRE 00100000000 –
Repeat cycles 1 through 4 until nRC - 1; truncate if needed
nRC ACT 001100000F0 –
nRC + 1 D 100000000F0 –
nRC + 2 D 100000000F0 –
nRC + 3 D# 111100000F0 –
nRC + 4 D# 111100000F0 –
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1; truncate if needed
nRC + nRCD RD 0 1 0 1 0 0 0 0 0 F 0 00110011
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1; truncate if needed
nRC + nRAS PRE 001000000F0 –
Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1; truncate if needed
1 2 × nRC Repeat sub-loop 0, use BA[2:0] = 1
2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2
3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3
4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4
5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5
6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6
7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7
Notes:
1. DQ, DQS, DQS# are midlevel unless driven as required by the RD command.
2. DM is LOW.
3. Burst sequence is driven on each DQ signal by the RD command.
4. Only selected bank (single) active.
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
29
Rev.2.0 June 2016
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