Datasheet

Electrical Specifications – I
DD
Specifications and Conditions
Within the following I
DD
measurement tables, the following definitions and conditions
are used, unless stated otherwise:
• LOW: V
IN
≤ V
IL(AC)max
; HIGH: V
IN
≥ V
IH(AC)min
.
• Midlevel: Inputs are V
REF
= V
DD
/2.
•R
ON
set to RZQ/7 (34Ω
•R
TT,nom
set to RZQ/6 (40Ω
•R
TT(WR)
set to RZQ/2 (120Ω
•Q
OFF
is enabled in MR1.
• ODT is enabled in MR1 (R
TT,nom
) and MR2 (R
TT(WR)
).
• TDQS is disabled in MR1.
• External DQ/DQS/DM load resistor is 25Ω to V
DDQ
/2.
• Burst lengths are BL8 fixed.
• AL equals 0 (except in I
DD7
).
•I
DD
specifications are tested after the device is properly initialized.
• Input slew rate is specified by AC parametric test conditions.
• Optional ASR is disabled.
• Read burst type uses nibble sequential (MR0[3] = 0).
• Loop patterns must be executed at least once before current measurements begin.
Table 8: Timing Parameters Used for I
DD
Measurements – Clock Units
I
DD
Parameter
DDR3L
-800
DDR3L
-1066
DDR3L
-1333
DDR3L
-1600
DDR3L
-1866
DDR3L
-2133
Unit
-25E -25
-18E -18
-15E -15
-12E -12 -10 -09
5-5-5 6-6-6 7-7-7 8-8-8 9-9-9 10-10-10 10-10-10 11-11-11 13-13-13 14-14-14
t
CK (MIN) I
DD
2.5 1.875 1.5 1.25 1.07 0.938 ns
CL I
DD
5678 9 10 10 11 13 14CK
t
RCD (MIN) I
DD
5678 9 10 10 11 13 14CK
t
RC (MIN) I
DD
20 21 27 28 33 34 38 39 45 50 CK
t
RAS (MIN) I
DD
15 15 20 20 24 24 28 28 32 36 CK
t
RP (MIN) 5678 9 10 10 11 13 14CK
t
FAW 20202727 30 30 32 32 33 38CK
t
RRD I
DD
4466 5 5 6 6 6 7CK
t
RFC 140 140 187 187 234 234 280 280 328 375 CK
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications – I
DD
Specifications and Conditions
27
Rev.2.0 June 2016
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