Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Input/Output Capacitance
Table 6: DDR3L Input/Output Capacitance
Note 1 applies to the entire table
Capacitance
Parameters
Sym
DDR3L
-800
DDR3L
-1066
DDR3L
-1333
DDR3L
-1600
DDR3L
-1866
DDR3L
-2133
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
CK and CK# C
CK
0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 0.8 1.3 0.8 1.3 pF
ΔC: CK to CK# C
DCK
0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15 pF
Single-end
I/O: DQ, DM
C
IO
1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 1.4 2.1 pF
2
Differential
I/O: DQS,
DQS#, TDQS,
TDQS#
C
IO
1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 1.4 2.1 1.4 2.1 pF
3
ΔC: DQS to
DQS#, TDQS,
TDQS#
C
DDQS
0.0 0.2 0.0 0.2 0.0 0.15 0.0 0.15 0.0 0.15 0.0 0.15
pF
3
ΔC: DQ to
DQS
C
DIO
–0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3 –0.5 0.3
pF
4
Inputs (CTRL,
CMD, ADDR)
C
I
0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2 0.75 1.2 pF
5
ΔC: CTRL to
CK
C
DI_CTRL
–0.5 0.3 –0.5 0.3 –0.4 0.2 –0.4 0.2 –0.4 0.2 –0.4 0.2
pF
6
ΔC:
CMD_ADDR
to CK
C
DI_CMD
_ADDR
–0.5 0.5 –0.5 0.5 –0.4 0.4 –0.4 0.4 –0.4 0.4 –0.4 0.4
pF
7
ZQ pin
capacitance
C
ZQ
– 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0
pF
Reset pin
capacitance
C
RE
– 3.0 – 3.0 – 3.0 – 3.0 – 3.0 – 3.0
pF
Notes:
1. V
DD
= 1.35V (1.283–1.45V), V
DDQ
= V
DD
, V
REF
= V
SS
, f = 100 MHz, T
C
= 25°C. V
OUT(DC)
= 0.5
× V
DDQ
, V
OUT
= 0.1V (peak-to-peak).
2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading.
3. Includes TDQS, TDQS#. C
DDQS
is for DQS vs. DQS# and TDQS vs. TDQS# separately.
4. C
DIO
= C
IO(DQ)
- 0.5 × (C
IO(DQS)
+ C
IO(DQS#)
).
5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR =
A[n:0], BA[2:0].
6. C
DI_CTRL
= C
I(CTRL)
- 0.5 × (C
CK(CK)
+ C
CK(CK#)
).
7. C
DI_CMD_ADDR
= C
I(CMD_ADDR)
- 0.5 × (C
CK(CK)
+ C
CK(CK#)
).
8Gb: x4, x8, x16 DDR3L SDRAM
Electrical Specifications
25
Rev.2.0 June 2016
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