Datasheet

Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol Type Description
RESET# Input Reset: RESET# is an active LOW CMOS input referenced to V
SS
. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
DD
and
DC LOW ≤ 0.2 × V
DDQ
. RESET# assertion and desertion are asynchronous.
UDM Input Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-
byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to V
REFDQ
.
DQ[7:0] I/O Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to V
REFDQ
.
DQ[15:8] I/O Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to V
REFDQ
.
LDQS, LDQS# I/O Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
UDQS, UDQS# I/O Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
V
DD
Supply Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible).
V
DDQ
Supply DQ power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible). Isola-
ted on the device for improved noise immunity.
V
REFCA
Supply Reference voltage for control, command, and address: V
REFCA
must be
maintained at all times (including self refresh) for proper device operation.
V
REFDQ
Supply Reference voltage for data: V
REFDQ
must be maintained at all times (excluding self
refresh) for proper device operation.
V
SS
Supply Ground.
V
SSQ
Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to V
SSQ
.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
8Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
21
Rev.2.0 June 2016
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