Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 118: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4
CK
CK#
CKE
Command
Don’t CareTransitioning
t
XPDLL
t
RFC (MIN)
NOP NOP NOP NOP NOP NOP NOP NOP NOPNOPREF NOP NOPNOP NOP
PDE transition period
PDX transition period
Indicates break
in time scale
t
ANPD
Short CKE low transition period (R
TT
change asynchronous or synchronous)
t
ANPD
Note:
1. AL = 0, WL = 5,
t
ANPD = 4.
Figure 119: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
CK
CK#
Command
Don’t CareTransitioning
NOP NOP NOPNOP NOP NOP NOP NOP NOP NOPNOPNOP NOP NOPNOP NOP
t
ANPD
t
XPDLL
Indicates break
in time scale
Ta0 Ta1 Ta2 Ta3 Ta4
CKE
t
ANPD
Short CKE HIGH transition period (R
TT
change asynchronous or synchonous)
Note:
1. AL = 0, WL = 5,
t
ANPD = 4.
8Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
207
Rev.2.0 June 2016
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