Datasheet

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
The DRAM’s ODT can exhibit either asynchronous or synchronous behavior during
power-down exit (PDX). This transition period occurs if the DLL is selected to be off
when in precharge power-down mode by setting MR0[12] to 0. Power-down exit begins
t
ANPD prior to CKE first being registered HIGH, and ends
t
XPDLL after CKE is first reg-
istered HIGH.
t
ANPD is equal to the greater of ODTLoff + 1
t
CK or ODTLon + 1
t
CK. The
transition period is
t
ANPD +
t
XPDLL.
ODT assertion during power-down exit results in an R
TT
change as early as the lesser of
t
AONPD (MIN) and ODTLon ×
t
CK +
t
AON (MIN), or as late as the greater of
t
AONPD
(MAX) and ODTLon ×
t
CK +
t
AON (MAX). ODT de-assertion during power-down exit
may result in an R
TT
change as early as the lesser of
t
AOFPD (MIN) and ODTLoff ×
t
CK +
t
AOF (MIN), or as late as the greater of
t
AOFPD (MAX) and ODTLoff ×
t
CK +
t
AOF (MAX).
Table 89 (page 203) summarizes these parameters.
If AL has a large value, the uncertainty of the R
TT
state becomes quite large. This is be-
cause ODTLon and ODTLoff are derived from WL, and WL is equal to CWL + AL. Fig-
ure 117 (page 205) shows three different cases:
• ODT C: Asynchronous behavior before
t
ANPD.
• ODT B: ODT state changes during the transition period, with
t
AOFPD (MIN) < ODTL-
off ×
t
CK +
t
AOF (MIN), and ODTLoff ×
t
CK +
t
AOF (MAX) >
t
AOFPD (MAX).
• ODT A: ODT state changes after the transition period with synchronous response.
8Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous to Synchronous ODT Mode Transition (Power-
Down Exit)
204
Rev.2.0 June 2016
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