Datasheet

Table 89: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period
Description Min Max Power-down entry transition period (power-down entry)
Greater of:
t
ANPD or
t
RFC - refresh to CKE LOW
Power-down exit transition period (power-down exit)
t
ANPD +
t
XPDLL
ODT to R
TT
turn-on delay
(ODTLon = WL - 2)
Lesser of:
t
AONPD (MIN) (2ns) or
ODTLon ×
t
CK +
t
AON (MIN)
Greater of:
t
AONPD (MAX) (8.5ns) or
ODTLon ×
t
CK +
t
AON (MAX)
ODT to R
TT
turn-off delay
(ODTLoff = WL - 2)
Lesser of:
t
AOFPD (MIN) (2ns) or
ODTLoff ×
t
CK +
t
AOF (MIN)
Greater of:
t
AOFPD (MAX) (8.5ns) or
ODTLoff ×
t
CK +
t
AOF (MAX)
t
ANPD WL - 1 (greater of ODTLoff + 1 or ODTLon + 1)
Figure 116: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
AOFPD (MAX)
ODTLoff
T10 T11 T12 T13 Ta0 Ta1 Ta3Ta2
CK
CK#
DRAM R
TT
B
asynchronous
or synchronous
R
TT,nom
DRAM R
TT
C
asynchronous
R
TT,nom
Don’t CareTransitioning
CKE
NOP NOP NOPNOP NOPCommand NOPREF NOP NOP NOP NOPNOP NOP NOP NOPNOP NOP NOP
PDE transition period
Indicates break in time scale
ODTLoff +
t
AOFPD (MIN)
t
AOFPD (MAX)
t
AOFPD (MIN)
ODTLoff +
t
AOFPD (MAX)
t
AOFPD (MIN)
t
ANPD
t
AOF (MIN)
t
AOF (MAX)
DRAM R
TT
A
synchronous
R
TT,nom
ODT A
synchronous
ODT C
asynchronous
ODT B
asynchronous
or synchronous
t
RFC (MIN)
Note:
1. AL = 0; CWL = 5; ODTL(off) = WL - 2 = 3.
8Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
203
Rev.2.0 June 2016
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