Datasheet

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)
There is a transition period around power-down entry (PDE) where the DRAM’s ODT
may exhibit either synchronous or asynchronous behavior. This transition period oc-
curs if the DLL is selected to be off when in precharge power-down mode by the setting
MR0[12] = 0. Power-down entry begins
t
ANPD prior to CKE first being registered LOW,
and ends when CKE is first registered LOW.
t
ANPD is equal to the greater of ODTLoff +
1
t
CK or ODTLon + 1
t
CK. If a REFRESH command has been issued, and it is in progress
when CKE goes LOW, power-down entry ends
t
RFC after the REFRESH command, rath-
er than when CKE is first registered LOW. Power-down entry then becomes the greater
of
t
ANPD and
t
RFC - REFRESH command to CKE registered LOW.
ODT assertion during power-down entry results in an R
TT
change as early as the lesser
of
t
AONPD (MIN) and ODTLon ×
t
CK +
t
AON (MIN), or as late as the greater of
t
AONPD
(MAX) and ODTLon ×
t
CK +
t
AON (MAX). ODT de-assertion during power-down entry
can result in an R
TT
change as early as the lesser of
t
AOFPD (MIN) and ODTLoff ×
t
CK +
t
AOF (MIN), or as late as the greater of
t
AOFPD (MAX) and ODTLoff ×
t
CK +
t
AOF (MAX).
Table 89 (page 203) summarizes these parameters.
If AL has a large value, the uncertainty of the state of R
TT
becomes quite large. This is
because ODTLon and ODTLoff are derived from the WL; and WL is equal to CWL + AL.
Figure 116 (page 203) shows three different cases:
• ODT_A: Synchronous behavior before
t
ANPD.
• ODT_B: ODT state changes during the transition period with
t
AONPD (MIN) <
ODTLon ×
t
CK +
t
AON (MIN) and
t
AONPD (MAX) > ODTLon ×
t
CK +
t
AON (MAX).
• ODT_C: ODT state changes after the transition period with asynchronous behavior.
8Gb: x4, x8, x16 DDR3L SDRAM
Asynchronous ODT Mode
202
Rev.2.0 June 2016
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