Datasheet

Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol Type Description
DQ[3:0] I/O Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to V
REFDQ
.
DQ[7:0] I/O Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to V
REFDQ
.
DQS, DQS# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS# Output Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.
V
DD
Supply Power supply: 1.35V (1.283–1.45V) / 1.5V ±0.075V (backward compatible).
V
DDQ
Supply DQ power supply: 1.35V (1.283–1.45V) /1.5V ±0.075V (backward compatible). Isola-
ted on the device for improved noise immunity.
V
REFCA
Supply Reference voltage for control, command, and address: V
REFCA
must be
maintained at all times (including self refresh) for proper device operation.
V
REFDQ
Supply Reference voltage for data: V
REFDQ
must be maintained at all times (excluding self
refresh) for proper device operation.
V
SS
Supply Ground.
V
SSQ
Supply DQ ground: Isolated on the device for improved noise immunity.
ZQ Reference External reference ball for output drive calibration: This ball is tied to an
external 240Ω resistor (RZQ), which is tied to V
SSQ
.
NC – No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF – No function: When configured as a x4 device, these balls are NF. When configured
as a x8 device, these balls are defined as TDQS#, DQ[7:4].
8Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
19
Rev.2.0 June 2016
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