Datasheet

Figure 110: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CK
CK#
ODTLcwn4
DQS, DQS#
Address Valid
Don’t CareTransitioning
ODTLoff
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
DQ
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
t
ADC (MIN)
t
AOF (MIN)
t
AOF (MAX)
t
ADC (MAX)
t
ADC (MAX)
t
AON (MIN)
ODTH4
ODT
R
TT
R
TT(WR)
R
TT,nom
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. R
TT,nom
and R
TT(WR)
are enabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon
ODTLcnw
WL
T10 T11
CK
CK#
ODTLcwn4
DQS, DQS#
Address
Valid
Command WRS4NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
Don’t CareTransitioning
DQ
DI
n
DI
n + 3
DI
n + 2
DI
n + 1
ODTH4
t
ADC (MAX)
t
AON (MIN)
t
AOF (MIN)
t
AOF (MAX)
ODTLoff
R
TT
R
TT(WR)
ODT
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. R
TT,nom
can be either enabled or disabled. If disabled,
ODT can remain HIGH. R
TT(WR)
is enabled.
2. In this example ODTH4 = 4 is satisfied exactly.
8Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
194
Rev.2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: [phone] FAX: [phone]