Datasheet

Table Of Contents
Figure 109: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLcwn8
ODTLon
ODTLcnw
WL
t
AOF (MAX)
T10 T11
CK
CK#
Address
R
TT
ODT
DQ
DQS, DQS#
DI
b + 3
DI
b + 2
DI
b + 1
DI
b
DI
b + 7
DI
b + 6
DI
b + 5
DI
b + 4
Valid
Don’t CareTransitioning
Command
WRS8NOP NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP
R
TT(WR)
ODTH8 ODTLoff
t
ADC (MAX)
t
AON (MIN)
t
AOF (MIN)
Notes:
1. Via MRS or OTF; AL = 0, CWL = 5. If R
TT,nom
can be either enabled or disabled, ODT can be HIGH. R
TT(WR)
is enabled.
2. In this example, ODTH8 = 6 is satisfied exactly.
8Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
193
Rev.2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211