Datasheet

Figure 107: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLon ODTLcwn4
ODTLcnw
WL
ODTLoff
T10 T11 T12 T13 T14 T15
T17
T16
CK
CK#
Command
Address
R
TT
ODT
DQ
DQS, DQS#
Valid
WRS4NOP NOP NOP NOP NOP NOP NOP
Don’t CareTransitioning
R
TT(WR)
R
TT,nom
R
TT,nom
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
NOP NOP NOP NOP NOP NOP NOP NOPNOP NOP
ODTH4
ODTH4
t
AON (MIN)
t
ADC (MIN)
t
ADC (MIN)
t
AOF (MIN)
t
AON (MAX)
t
ADC (MAX)
t
ADC (MAX)
t
AOF (MAX)
Notes:
1. Via MRS or OTF. AL = 0, CWL = 5. R
TT,nom
and R
TT(WR)
are enabled.
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
Figure 108: Dynamic ODT: Without WRITE Command
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
ODTLoff
T10 T11
CK
CK#
R
TT
Don’t CareTransitioning
Command
Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Address
DQS, DQS#
DQ
ODTH4
ODTLon
t
AON (MAX)
t
AON (MIN)
t
AOF (MIN)
t
AOF (MAX)
ODT
R
TT,nom
Notes:
1. AL = 0, CWL = 5. R
TT,nom
is enabled and R
TT(WR)
is either enabled or disabled.
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg-
istered LOW at T5 is also legal.
8Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
192
Rev.2.0 June 2016
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