Datasheet

Table 85: Mode Registers for R
TT(WR)
MR2 (R
TT(WR)
)
R
TT(WR)
(RZQ) R
TT(WR)
(Ohm)M10 M9
0 0 Dynamic ODT off: WRITE does not affect R
TT,nom
0 1 RZQ/4 60
1 0 RZQ/2 120
1 1 Reserved Reserved
Table 86: Timing Diagrams for Dynamic ODT
Figure and Page Title
Figure 107 (page 192) Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Figure 108 (page 192) Dynamic ODT: Without WRITE Command
Figure 109 (page 193) Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Figure 110 (page 194) Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 111 (page 194) Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
8Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
191
Rev.2.0 June 2016
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