Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
• During DRAM operation without READ or WRITE commands, the termination is con-
trolled.
– Nominal termination strength R
TT,nom
is used.
– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and
ODTLoff.
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
and if dynamic ODT is enabled, the ODT termination is controlled.
– A latency of ODTLcnw after the WRITE command: termination strength R
TT,nom
switches to R
TT(WR)
– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)
after the WRITE command: termination strength R
TT(WR)
switches back to R
TT,nom
.
– On/off termination timing is controlled via the ODT ball and determined by ODT-
Lon, ODTLoff, ODTH4, and ODTH8.
– During the
t
ADC transition window, the value of R
TT
is undefined.
ODT is constrained during writes and when dynamic ODT is enabled (see the table be-
low, Dynamic ODT Specific Parameters). ODT timings listed in the ODT Parameters ta-
ble in On-Die Termination (ODT) also apply to dynamic ODT mode.
Table 83: Dynamic ODT Specific Parameters
Symbol Description Begins at Defined to
Definition for All
DDR3L Speed
Bins
Unit
ODTLcnw Change from R
TT,nom
to
R
TT(WR)
Write registration R
TT
switched from R
TT,nom
to R
TT(WR)
WL - 2
t
CK
ODTLcwn4 Change from R
TT(WR)
to
R
TT,nom
(BC4)
Write registration R
TT
switched from R
TT(WR)
to R
TT,nom
4
t
CK + ODTL off
t
CK
ODTLcwn8 Change from R
TT(WR)
to
R
TT,nom
(BL8)
Write registration R
TT
switched from R
TT(WR)
to R
TT,nom
6
t
CK + ODTL off
t
CK
t
ADC R
TT
change skew ODTLcnw completed R
TT
transition complete 0.5
t
CK ± 0.2
t
CK
t
CK
Table 84: Mode Registers for R
TT,nom
MR1 (R
TT,nom
)
R
TT,nom
(RZQ) R
TT,nom
(Ohm) R
TT,nom
Mode RestrictionM9 M6 M2
0 0 0 Off Off n/a
0 0 1 RZQ/4 60 Self refresh
0 1 0 RZQ/2 120
0 1 1 RZQ/6 40
1 0 0 RZQ/12 20 Self refresh, write
1 0 1 RZQ/8 30
1 1 0 Reserved Reserved n/a
1 1 1 Reserved Reserved n/a
Note:
1. RZQ = 240Ω. If R
TT,nom
is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
8Gb: x4, x8, x16 DDR3L SDRAM
Dynamic ODT
190
Rev.2.0 June 2016
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