Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 105: RESET Sequence
T = 10ns (MIN)
T = 100ns (MIN)
T = 500μs (MIN)
t
XPR
t
MRD
t
MRD
t
MRD
t
MOD
t
CK
t
IOZ = 20ns
CKE
R
TT
BA[2:0]
All voltage
supplies valid
and stable
High-Z
DM
DQS
High-Z
Address
A10
CK
CK#
t
CL
Command
NOP
T0
Ta0
Don’t Care
t
CL
ODT
DQ
High-Z
Tb0
t
DLLK
MR1 with
DLL ENABLE
MRSMRS
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
Code Code
Code Code
Valid
Valid
Valid
Valid
Normal
operation
MR2
MR3
MRSMRS
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
Code Code
Code Code
Tc0 Td0
RESET#
Stable and
valid clock
Valid
DRAM ready
for external
commands
T1
t
ZQinit
A10 = H
ZQCL
t
IS
Valid
System RESET
(warm boot)
ZQCAL
MR0 with
DLL RESET
Indicates break
in time scale
t
CKSRX
1
t
IS
t
IS
t
IS
Static LOW in case R
TT_Nom
is enabled at time Ta0, otherwise static HIGH or LOW
Note:
1. The minimum time required is the longer of 10ns or 5 clocks.
8Gb: x4, x8, x16 DDR3L SDRAM
RESET Operation
186
Rev.2.0 June 2016
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