Datasheet

RESET Operation
The RESET signal (RESET#) is an asynchronous reset signal that triggers any time it
drops LOW, and there are no restrictions about when it can go LOW. After RESET# goes
LOW, it must remain LOW for 100ns. During this time, the outputs are disabled, ODT
(R
TT
) turns off (High-Z), and the DRAM resets itself. CKE should be driven LOW prior to
RESET# being driven HIGH. After RESET# goes HIGH, the DRAM must be re-initialized
as though a normal power-up was executed. All counters, except refresh counters, on
the DRAM are reset, and data stored in the DRAM is assumed unknown after RESET#
has gone low.
8Gb: x4, x8, x16 DDR3L SDRAM
RESET Operation
185
Rev.2.0 June 2016
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