Datasheet

exit mode precharge power-down. A summary of the two power-down modes is listed in
Table 79 (page 178).
While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable
clock signal must be maintained. ODT must be in a valid state but all other input signals
are “Don’t Care.” If RESET# goes LOW during power-down, the DRAM will switch out of
power-down mode and go into the reset state. After CKE is registered LOW, CKE must
remain LOW until
t
PD (MIN) has been satisfied. The maximum time allowed for power-
down duration is
t
PD (MAX) (9 ×
t
REFI).
The power-down states are synchronously exited when CKE is registered HIGH (with a
required NOP or DES command). CKE must be maintained HIGH until
t
CKE has been
satisfied. A valid, executable command may be applied after power-down exit latency,
t
XP, and
t
XPDLL have been satisfied. A summary of the power-down modes is listed be-
low.
For specific CKE-intensive operations, such as repeating a power-down-exit-to-refresh-
to-power-down-entry sequence, the number of clock cycles between power-down exit
and power-down entry may not be sufficient to keep the DLL properly updated. In addi-
tion to meeting
t
PD when the REFRESH command is used between power-down exit
and power-down entry, two other conditions must be met. First,
t
XP must be satisfied
before issuing the REFRESH command. Second,
t
XPDLL must be satisfied before the
next power-down may be entered. An example is shown in Figure 104 (page 184).
Table 79: Power-Down Modes
DRAM State MR0[12] DLL State
Power-
Down Exit
Relevant Parameters
Active (any bank open) “Don’t Care” On Fast
t
XP to any other valid command
Precharged
(all banks precharged)
1 On Fast
t
XP to any other valid command
0 Off Slow
t
XPDLL to commands that require the DLL to be
locked (READ, RDAP, or ODT on);
t
XP to any other valid command
8Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
178
Rev.2.0 June 2016
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