Datasheet

Power-Down Mode
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down I
DD
specifications are not applicable
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 78). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 94 (page 179) through Figure 103 (page 183).
Table 78: Command to Power-Down Entry Parameters
DRAM Status
Last Command Prior to
CKE LOW
1
Parameter (Min) Parameter Value Figure
Idle or active ACTIVATE
t
ACTPDEN 1
t
CK Figure 101 (page 182)
Idle or active PRECHARGE
t
PRPDEN 1
t
CK Figure 102 (page 183)
Active READ or READAP
t
RDPDEN RL + 4
t
CK + 1
t
CK Figure 97 (page 180)
Active WRITE: BL8OTF, BL8MRS,
BC4OTF
t
WRPDEN WL + 4
t
CK +
t
WR/
t
CK Figure 98 (page 181)
Active WRITE: BC4MRS WL + 2
t
CK +
t
WR/
t
CK Figure 98 (page 181)
Active WRITEAP: BL8OTF, BL8MRS,
BC4OTF
t
WRAPDEN WL + 4
t
CK + WR + 1
t
CK Figure 99 (page 181)
Active WRITEAP: BC4MRS WL + 2
t
CK + WR + 1
t
CK Figure 99 (page 181)
Idle REFRESH
t
REFPDEN 1
t
CK Figure 100 (page 182)
Power-down REFRESH
t
XPDLL Greater of 10
t
CK or 24ns Figure 104 (page 184)
Idle MODE REGISTER SET
t
MRSPDEN
t
MOD Figure 103 (page 183)
Note:
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous
t
ANPD prior to CKE going LOW and remains asynchronous until
t
ANPD +
t
XPDLL after CKE goes HIGH.
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until
t
CPDED has been satis-
fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 200) for detailed ODT usage requirements in slow
8Gb: x4, x8, x16 DDR3L SDRAM
Power-Down Mode
177
Rev.2.0 June 2016
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