Datasheet

Figure 93: Self Refresh Entry/Exit Timing
CK
CK#
Command
NOP
NOP
4
SRE (REF)
3
Address
CKE
ODT
2
RESET#
2
Valid
Valid
6
SRX (NOP)
NOP
5
t
RP
8
t
XSDLL
7, 9
ODTL
t
IS
t
CPDED
t
IS
t
IS
Enter self refresh mode
(synchronous)
Exit self refresh mode
(asynchronous)
T0 T1 T2 Tc0 Tc1 Td0Tb0
Don’t Care
Te0
Valid
Valid
7
Valid
Valid Valid
t
IH
Ta0
Tf0
Indicates break
in time scale
t
CKSRX
1
t
CKSRE
1
t
XS
6, 9
t
CKESR (MIN)
1
Notes:
1. The clock must be valid and stable, meeting
t
CK specifications at least
t
CKSRE after en-
tering self refresh mode, and at least
t
CKSRX prior to exiting self refresh mode, if the
clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and
unchanged from entry and during self refresh mode, then
t
CKSRE and
t
CKSRX do not
apply; however,
t
CKESR must be satisfied prior to exiting at SRX.
2. ODT must be disabled and R
TT
off prior to entering self refresh at state T1. If both
R
TT,nom
and R
TT(WR)
are disabled in the mode registers, ODT can be a “Don’t Care.”
3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW.
4. A NOP or DES command is required at T2 after the SRE command is issued prior to the
inputs becoming “Don’t Care.”
5. NOP or DES commands are required prior to exiting self refresh mode until state Te0.
6.
t
XS is required before any commands not requiring a locked DLL.
7.
t
XSDLL is required before any commands requiring a locked DLL.
8. The device must be in the all banks idle state prior to entering self refresh mode. For
example, all banks must be precharged,
t
RP must be met, and no data bursts can be in
progress.
9. Self refresh exit is asynchronous; however,
t
XS and
t
XSDLL timings start at the first rising
clock edge where CKE HIGH satisfies
t
ISXR at Tc1.
t
CKSRX timing is also measured so that
t
ISXR is satisfied at Tc1.
8Gb: x4, x8, x16 DDR3L SDRAM
SELF REFRESH Operation
175
Rev.2.0 June 2016
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