Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Figure 88: WRITE (BC4 OTF) to READ (BC4 OTF)
WL = 5 RL = 5
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
WPRE
T10 T11
Don’t CareTransitioning Data
Tn
NOPWRITE READ
ValidValid
NOP NOP NOP NOP NOP NOP NOP NOPNOP
CK
CK#
Command
1
DQ
4
DQS, DQS#
Address
3
t
WPST
t
BL = 4 clocks
NOP
t
WTR
2
Indicates break
in time scale
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2.
t
WTR controls the WRITE-to-READ delay to the same device and starts after
t
BL.
3. The BC4 OTF setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the READ
command at Tn.
4. DI n = data-in for column n.
5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
170
Rev 2.0 June 2016
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