Datasheet

Figure 87: WRITE to READ (BC4 Mode Register Setting)
WL = 5
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0
Don’t CareTransitioning Data
NOPWRITE
Valid
READ
Valid
NOP NOP NOP NOP NOP NOP NOPNOP
CK
CK#
Command
1
DQ
4
DQS, DQS#
Address
3
t
WPST
t
WTR
2
t
WPRE
Indicates break in time scale
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2.
t
WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T7.
3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at
Ta0.
4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5).
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
169
Rev 2.0 June 2016
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