Datasheet

Figure 85: Nonconsecutive WRITE to WRITE
CK
CK#
Command
NOP NOP NOP
Address
DQ
DM
DQS, DQS#
Transitioning Data
NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
NOPWRITE NOP WRITE
Valid
Valid
NOP
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
DI
n + 4
DI
n + 5
DI
n + 6
Don't Care
DI
n + 7
DI
b
DI
b + 1
DI
b + 2
DI
b + 3
DI
b + 4
DI
b + 5
DI
b + 6
DI
b + 7
WL = CWL + AL = 7
WL = CWL + AL = 7
Notes:
1. DI n (or b) = data-in for column n (or column b). 2. Seven subsequent elements of data-in are applied in the programmed order following DO n. 3. Each WRITE command may be to any bank. 4. Shown for WL = 7 (CWL = 7, AL = 0).
Figure 86: WRITE (BL8) to READ (BL8)
WL = 5
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9
t
WPRE
T10 T11
Don’t Care
Transitioning Data
Ta0
NOP
WRITE
READ
Valid
Valid
NOP NOP
NOP NOP
NOP NOP NOP
NOPNOP
NOP
CK
CK#
Command
1
DQ
4
DQS, DQS#
Address
3
t
WPST
t
WTR
2
Indicates break in time scale
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2.
t
WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last
write data shown at T9.
3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command
at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0.
4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
168
Rev 2.0 June 2016
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