Datasheet

Figure 82: WRITE Burst
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Don’t Care
Transitioning Data
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
Bank,
Col n
NOP
WRITE
NOP
NOP NOP
NOP NOP
NOP NOP NOP
NOP
CK
CK#
Command
1
DQ
3
DQS, DQS#
Address
2
t
WPST
t
WPRE
t
WPST
t
DQSL
DQ
3
DQ
3
t
WPST
DQS, DQS#
DQS, DQS#
t
DQSL
t
WPRE
t
DQSS
t
DQSS
t
DSH
t
DSH
t
DSH
t
DSH
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSS
t
DSH
t
DSH
t
DSH
t
DSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSH
t
DQSL
t
DQSL
t
DQSL
t
DQSL
t
DQSH
t
DQSH
t
DQSH
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSL
t
DQSH
t
DQSH
WL = AL + CWL
t
DQSS (MIN)
t
DQSS (NOM)
t
DQSS (MAX)
t
DQSL
t
WPRE
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
DI
n + 3
DI
n + 2
DI
n + 1
DI
n
DI
n + 7
DI
n + 6
DI
n + 5
DI
n + 4
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
the WRITE command at T0.
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
t
DQSS must be met at each rising clock edge.
6.
t
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
t
WPST ac-
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
8Gb: x4, x8, x16 DDR3L SDRAM
WRITE Operation
166
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070
TEL: [phone] FAX: [phone]