Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Figure 77: Method for Calculating
t
LZ and
t
HZ
t
HZDQS,
t
HZDQ
t
HZDQS,
t
HZDQ end point = 2 × T1 - T2
V
OH
- xmV
V
TT
- xmV
V
OL
+ xmV
V
TT
+ xmV
V
OH
- 2xmV
V
TT
- 2xmV
V
OL
+ 2xmV
V
TT
+ 2xmV
t
LZDQS,
t
LZDQ
t
LZDQS,
t
LZDQ begin point = 2 × T1 - T2
T1
T1
T2
T2
Notes:
1. Within a burst, the rising strobe edge is not necessarily fixed at
t
DQSCK (MIN) or
t
DQSCK
(MAX). Instead, the rising strobe edge can vary between
t
DQSCK (MIN) and
t
DQSCK
(MAX).
2. The DQS HIGH pulse width is defined by
t
QSH, and the DQS LOW pulse width is defined
by
t
QSL. Likewise,
t
LZDQS (MIN) and
t
HZDQS (MIN) are not tied to
t
DQSCK (MIN) (early
strobe case), and
t
LZDQS (MAX) and
t
HZDQS (MAX) are not tied to
t
DQSCK (MAX) (late
strobe case); however, they tend to track one another.
3. The minimum pulse width of the READ preamble is defined by
t
RPRE (MIN). The mini-
mum pulse width of the READ postamble is defined by
t
RPST (MIN).
Figure 78:
t
RPRE Timing
t
RPRE
DQS - DQS#
DQS
DQS#
T1
t
RPRE begins
T2
t
RPRE ends
CK
CK#
V
TT
Resulting differential
signal relevant for
t
RPRE specification
t
C
t
A
t
B
t
D
Single-ended signal provided
as background information
0V
Single-ended signal provided
as background information
V
TT
V
TT
8Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
162
Rev 2.0 June 2016
© 2015 Alliance Memory, Inc. All rights reserved.
Alliance Memory Inc. reserves the right to change products or specification without notice
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