Datasheet

DQS to DQ output timing is shown in Figure 75 (page 160). The DQ transitions between
valid data outputs must be within
t
DQSQ of the crossing point of DQS, DQS#. DQS must
also maintain a minimum HIGH and LOW time of
t
QSH and
t
QSL. Prior to the READ
preamble, the DQ balls will either be floating or terminated, depending on the status of
the ODT signal.
Figure 76 (page 161) shows the strobe-to-clock timing during a READ. The crossing
point DQS, DQS# must transition within ±
t
DQSCK of the clock crossing point. The data
out has no timing relationship to CK, only to DQS, as shown in Figure 76 (page 161).
Figure 76 (page 161) also shows the READ preamble and postamble. Typically, both
DQS and DQS# are High-Z to save power (V
DDQ
). Prior to data output from the DRAM,
DQS is driven LOW and DQS# is HIGH for
t
RPRE. This is known as the READ preamble.
The READ postamble,
t
RPST, is one half clock from the last DQS, DQS# transition. Dur-
ing the READ postamble, DQS is driven LOW and DQS# is HIGH. When complete, the
DQ is disabled or continues terminating, depending on the state of the ODT signal. Fig-
ure 79 (page 163) demonstrates how to measure
t
RPST.
8Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
159
Rev 2.0 June 2016
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