Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 4: 1 Gig x 8 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
16
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
11
Command
decode
A[15:0]
BA[2:0]
16
19
16384
I/O gating
DM mask logic
Column
decoder
Bank 0
Memory
array
(65,536 x 256 x 64)
Bank 0
row-
address
latch
and
decoder
65,536
Sense amplifiers
Bank
control
logic
19
Bank 1
Bank 2
Bank 3
16
8
3
3
Refresh
counter
8
64
64
64
DQS, DQS#
Columns 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
Read
drivers
DQ[7:0]
READ
FIFO
and
data
MUX
Data
8
3
Bank 1
Bank 2
Bank 3
DM/TDQS
(shared pin)
TDQS#
CK, CK#
DQS/DQS#
ZQ CAL
ZQ
RZQ
ODT
CKE
CK, CK#
RAS#
WE#
CAS#
CS#
RESET#
CK, CK#
DLL
DQ[7:0]
DQ8
(1 . . . 8)
(1, 2)
sw1 sw2
V
DDQ
/2
R
TT(WR)
R
TT,nom
sw1 sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
sw1 sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
BC4 (burst chop)
BC4
BC4
Write
drivers
and
input
logic
Data
interface
Column 2
(select upper or
lower nibble for BC4)
(256
x64)
ODT
control
Address
register
A12
V
SSQ
OTF
OTF
Figure 5: 512 Meg x 16 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
16
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
10
Command
decode
A[15:0]
BA[2:0]
16
Address
register
18
(128
x128)
16,384
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
(65,536 x 128 x 128)
Bank 0
row-
address
latch
and
decoder
65,536
Sense amplifiers
Bank
control
logic
19
Bank 1
Bank 2
Bank 3
16
7
3
3
Refresh
counter
16
128
128
128
LDQS, LDQS#, UDQS, UDQS#
Column 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To ODT/output drivers
BC4
READ
drivers
DQ[15:0]
READ
FIFO
and
data
MUX
Data
16
BC4 (burst chop)
3
Bank 1
Bank 2
Bank 3
LDM/UDM
CK, CK#
LDQS, LDQS#
UDQS, UDQS#
ZQ CAL
ZQ
RZQ
ODT
CKE
CK, CK#
RAS#
WE#
CAS#
CS#
RESET#
CK, CK#
DLL
DQ[15:0]
(1 . . . 16)
(1 . . . 4)
(1, 2)
sw1
sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
BC4
sw1
sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
sw1
sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
Column 2
(select upper or
lower nibble for BC4)
Data
interface
WRITE
drivers
and
input
logic
ODT
control
V
SSQ
A12
OTF
OTF
8Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
15
Rev.2.0 June 2016
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