Datasheet

Figure 72: READ to PRECHARGE (BC4)
CK
CK#
Don’t CareTransitioning Data
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
Command
NOP NOP NOP NOP NOP NOP NOP NOP NOP ACT NOP NOP
NOP NOP
NOPREAD NOP PRE
Address
Bank a,
Col n
Bank a,
(or all)
Bank a,
Row b
t
RP
t
RTP
DQS, DQS#
DQ
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
t
RAS
Figure 73: READ to PRECHARGE (AL = 5, CL = 6)
CK
CK#
Command
NOP NOP NOP NOP
Address
DQ
DQS, DQS#
Don’t CareTransitioning Data
NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
NOPREAD
Bank a,
Col n
NOP
PRE
Bank a,
(or all)
ACT
Bank a,
Row b
NOP
NOP
t
RAS
CL = 6
AL = 5
t
RTP
t
RP
DO
n + 3
DO
n + 2
DO
n
DO
n + 1
Figure 74: READ with Auto Precharge (AL = 4, CL = 6)
CK
CK#
Command NOP NOP NOP NOP
Address
DQ
DQS, DQS#
Don’t CareTransitioning Data
NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0
t
RTP (MIN)
NOPREAD NOP
AL = 4
NOP NOP
CL = 6
NOP
t
RAS (MIN)
ACT
Indicates break in time scale
t
RP
Bank a,
Col n
Bank a,
Row b
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
8Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
158
Rev 2.0 June 2016
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