Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Figure 70: READ (BC4) to WRITE (BC4) OTF
Don’t CareTransitioning Data
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CK
CK#
Address
2
Command
1
t
WPST
t
WPRE
t
RPST
DQS, DQS#
DQ
3
WL = 5
t
WR
t
WTR
t
BL = 4 clocks
t
RPRE
RL = 5
READ-to-WRITE command delay = RL +
t
CCD/2 + 2
t
CK - WL
READ
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DI
n
DI
n + 1
DI
n + 2
DI
n + 3
Bank,
Col b
Bank,
Col n
NOP NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these times.
2. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at
T4.
3. DO n = data-out from column n; DI n = data-in from column b.
4. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5).
Figure 71: READ to PRECHARGE (BL8)
t
RAS
t
RTP
CK
CK#
Command
NOP NOP NOP NOP
Address
DQ
DQS, DQS#
Don’t CareTransitioning Data
NOP NOP NOP NOP NOP ACT NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
NOPREAD
Bank a,
Col n
NOP PRE
Bank a,
(or all)
Bank a,
Row b
t
RP
DO
n
DO
n + 1
DO
n + 2
DO
n + 3
DO
n + 4
DO
n + 5
DO
n + 6
DO
n + 7
8Gb: x4, x8, x16 DDR3L SDRAM
READ Operation
157
Rev 2.0 June 2016
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