Datasheet

Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 2 Gig x 4 Functional Block Diagram
Bank 5
Bank 6
Bank 7
Bank 4
Bank 7
Bank 4
Bank 5
Bank 6
16
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Mode registers
12
Command
decode
A[15:0]
BA[2:0]
16
Address
register
19
512
(x32)
16,384
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
(65,536 x 512 x 32)
Bank 0
row-
address
latch
and
decoder
65,536
Sense amplifiers
Bank
control
logic
19
Bank 1
Bank 2
Bank 3
16
9
3
3
Refresh
counter
4
32
32
32
DQS, DQS#
Columns 0, 1, and 2
Columns 0, 1, and 2
ZQCL, ZQCS
To pull-up/pull-down
networks
READ
drivers
DQ[3:0]
READ
FIFO
and
data
MUX
Data
4
3
Bank 1
Bank 2
Bank 3
DM
DM
CK, CK#
DQS, DQS#
ZQ CAL
CS#
ZQ
RZQ
CK, CK#
RAS#
WE#
CAS#
ODT
CKE
RESET#
CK, CK#
DLL
DQ[3:0]
(1 . . . 4)
(1, 2)
sw1
sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
sw1 sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
sw1
sw2
V
DDQ
/2
R
TT,nom
R
TT(WR)
OTF
BC4 (burst chop)
BC4
Column 2
(select upper or
lower nibble for BC4)
Data
interface
WRITE
drivers
and
input
logic
ODT
control
V
SSQ
A12
OTF
BC4
8Gb: x4, x8, x16 DDR3L SDRAM
Functional Block Diagrams
14
Rev 2.0 June 2016
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