Datasheet

Figure 61: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble
T0 Ta Tb
01A10/AP Valid Valid 0
CK
CK#
MRSPREA
READ
1
READ
1
NOP NOP NOP NOP NOP NOP NOP MRS NOP NOP ValidCommand
0
0
4
1
3
1A2
t
MOD
t
MPRR
3 Valid 3Bank address Valid
0
2
0
2
0A[1:0] Valid
00A[15:13] Valid Valid 00A11 Valid Valid
0000A[9:3] Valid Valid
Don’t Care
Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td
Indicates break in time scale
RL
DQ
DQS, DQS#
0A12/BC#
Valid
1
Valid
1
0
RL
t
RF
t
MOD
t
CCD
Notes:
1. READ with BC4 either by MRS or OTF. 2. Memory controller must drive 0 on A[1:0]. 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. 4. A2 = 0 selects lower 4 nibble bits 0 . . . 3.
8Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
148
Rev 2.0 June 2016
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