Datasheet
Table Of Contents
- DDR3L SDRAM
- Description
- State Diagram
- Functional Description
- Functional Block Diagrams
- Ball Assignments and Descriptions
- Package Dimensions
- Electrical Specifications
- Thermal Characteristics
- Electrical Specifications – I DD Specifications and Conditions
- Electrical Characteristics – 1.35V IDD Specifications
- Electrical Specifications – DC and AC
- ODT Characteristics
- Output Driver Impedance
- Output Characteristics and Operating Conditions
- Speed Bin Tables
- Electrical Characteristics and AC Operating Conditions
- Electrical Characteristics and AC Operating Conditions
- Command and Address Setup, Hold, and Derating
- Data Setup, Hold, and Derating
- Commands – Truth Tables
- Commands
- Input Clock Frequency Change
- Write Leveling
- Initialization
- Voltage Initialization / Change
- Mode Registers
- Mode Register 0 (MR0)
- Mode Register 1 (MR1)
- Mode Register 2 (MR2)
- Mode Register 3 (MR3)
- MODE REGISTER SET (MRS) Command
- ZQ CALIBRATION Operation
- ACTIVATE Operation
- READ Operation
- WRITE Operation
- PRECHARGE Operation
- SELF REFRESH Operation
- Extended Temperature Usage
- Power-Down Mode
- RESET Operation
- On-Die Termination (ODT)
- Dynamic ODT
- Synchronous ODT Mode
- Asynchronous ODT Mode
- Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout
T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Td
CK
CK#
t
MPRR
Don’t Care
Indicates break
in time scale
RL
3 Valid 3Bank address Valid
A[1:0] Valid
0
2
0
2
0
A2
1
2
0
2
1 0
0A[15:13] Valid Valid 0
A[9:3] Valid Valid 0000
A11 Valid Valid 00
A12/BC#
Valid
1
00
A10/AP Valid Valid 001
RL
PREA
READ
1
NOP NOP NOP NOP NOP NOP NOP NOP NOP MRS ValidCommand
READ
1
MRS
DQ
Valid
DQS, DQS#
t
RP
t
MOD
t
CCD
t
MOD
Notes:
1. READ with BL8 either by MRS or OTF.
2. Memory controller must drive 0 on A[2:0].
8Gb: x4, x8, x16 DDR3L SDRAM
Mode Register 3 (MR3)
146
Rev 2.0 June 2016
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